Backend

rvmyth integration with PLL, DAC and SRAM using Sky130

{Project code - RPDS}

RISC-V based SoC design, implementation and tapeout using VSD Sky130 IPs

Performance characterization for VSDBabySoC comprising of RISC-V core, PLL and DAC

{Project code - PCVRPD}

Analyze and characterize RISC-V based VSDBabySoC for all timing corners, fix timing violations, ECO, implement and tapeout

rvmyth : RTL2GDS with OpenLane with the standard cells from Libresilicon StdCellLib generated standard cells for SKY130   

{Project Code:ROLS}

Take the LibreSilicon Standard Cells for the SKY130 process (https://pdk.libresilicon.com/dist/StdCellLib_20210618/Catalog/buildreport.html) and synthesize a RVMYTH design using those standard cells with OpenLane, preferably directly into an EFabless Caravel User-Space.

FPGA

1st CLaaS for Local FPGAs

{Project code - 1CLF}

1st Class supports web application communication with FPGA logic in the cloud. Support local FPGA use cases as well. This is useful for local applications as well as to support development that will ultimately be deployed to the cloud.

World CLaaS: Open FPGA Cloud

{Project code - WCOFC}

The vision is to enable individuals with FPGAs (World CLaaS Citizens) to share their hardware with the world

WARP-V Many-core Accelerator Microservice

{Project Code - WMAM}

It will provide a configurable, easily-modifiable many-core-on-FPGA hardware accelerator deployed as a microservice to accelerate web and cloud applications.