RISC-V

Visualization of SweRV

{Project code - VOS}

The SweRV core is an open-source SystemVerilog RISC-V CPU core developed by Western Digital. It is an interesting core for college course and is being highlighted in the RVfpga course for one. Visualizing the operation of the core can greatly enhance the learning experience. This project aims to do so. SweRV is be built and simulated within Makerchip

Implementing other ISAs in WARP-V

{Project Code - IIW}

WARP-V currently has support for RISC-V, (incomplete) MIPS, and a toy educational ISA. PowerPC is also open now and could be implemented, in addition to any other open ISAs.

Neural Net

{Project code - NN}

We have created a simple configurable neural network model in TL-Verilog. This could follow a similar path to WARP-V w/ a configurator and cloud FPGA implementation. The WARP-V configurator is build in a modular fashion to support this easily.

TensorCore Accelerator for Machine Learning

{Project code - TCAML}

This project focuses on implementing a Deep Learning hardware accelerator called TensorCore - which is a Vector Processor based on v0.10 of the open source RISCV Vector ISA. It is expected to serve as a proof-point for a Deep Learning research platform to experiment with tensor operators and custom number systems

Analog

High Frequency analog VCO design and implementation using Sky130

{Project code : KCEDVCO}

200MHz, 400MHz and 915MHz VCO design using Sky130nm - from specification to tapeout

Low Dropout Regulation :A low-dropout regulator (LDO) is a DC linear voltage regulator that can regulate the output 
voltage that is powered from a higher voltage input. 

{Project Code:LDO}

LDO  Specifications:
1.     Technology: Google Sky water 130nm 
2.     Input power supply range: 2-to-5 V
3.     Output Voltage: 1.8 V
4.     Load current: 10 mA
5.     Temp range: -40 to 125 Degree cent.
6.     Circuit current: 0.5 mA
7.     Reference Voltage: 1.2 V @ < 50 ppm