Hi
Despite of having so many free resources on RISC-V micro-architecture design courses around the globe, VSD is proud to say that customers found our paid RISC-V based MYTH (microprocessor for you in thirty hours) 5-day workshop as the most structured one which hand-holds anyone and everyone who wants to learn
RISC-V ISA and RISC-V u-arch design from scratch. We had examples of 12/13-yr old students taking this workshop. Making workshops or courses free is more challenging as now you would have many eyes viewing your content, and one glitch in delivery might impact your brand. That's the reason, VSD free content and workshops are even more carefully curated.
RISC-V based MYTH workshop last day for registration - 29th November, 11:59pm IST, 2021
Workshop Day wise Content :
Day 1 : Introduction to RISC-V ISA and GNU compiler tool-chain
- Introduction to RISC-V basic keywords
- Lab-work for RISC-V software tool-chain
- Integer number representation
- Signed and unsigned arithmetic operations
Day 2: Introduction to ABI and basic verification flow
- Application Binary interface (ABI)
- Lab work using ABI function calls
- Basic verification flow using iverilog
Day 3: Digital Logic with TL-Verilog and Makerchip
- Combinational logic in TL-Verilog using Makerchip
- Sequential and pipe-lined logic
- Validity
- Hierarchy
Day 4: Basic RISC-V CPU micro-architecture
- Micro-architecture and test-bench for a simple RISC-V CPU
- Fetch, decode, and execute logic
- RISC-V control logic
Day 5: Complete Pipe-lined RISC-V CPU micro-architecture/store
- Pipe-lining the CPU
- Load and store instructions and memory
- Completing the RISC-V CPU
- Wrap-up and future opportunities
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