It takes time to build anything great. We did run into obstacles, but quality of perseverance overcomes almost everything
Building content for the "Tapeout Program" for the global semiconductor community really needed a good team of passionate industry leaders who are not only experts in their domain, but also share a similar vision. It is easy to find STA engineers, but (and this "but" comes with capital "B") it's really challenging to find STA leaders. Though I had enough experience doing STA in my previous
jobs from device physics point of view, VSD needed to be fair with the community for such an important topic and decided to look for trusted partners.
VSD got lucky once again to have met Vikas Sachdeva - VLSI coach, trainer, Innovator, Speaker, Bachelor's from IIT Delhi and moreover an amazing human being. He got 8 publications and 2 patents under his belt. Vikas runs a very popular website "vlsideepdive" where he is an advisor for early stage products, courses, driving innovation in
edtech, learning methods, professional training and coaching
The Indian government is pushing hard to propel innovation, build domestic capacities to ensure hardware sovereignty, and build a Semiconductor ecosystem that requires 85,000+ highly trained engineers. This engagement with Vikas is just the beginning of a long term relationship and we plan to work
together deeply on Next gen VLSI EdTech which would cater to the needs of Indian semiconductor ecosystem
Take a look at "Workshop Content" below. We will introduce you to Vikas and his lab based content during the workshop. All the best and happy learning
| Day1 Lectures
1. STA Definition
2. Timing Paths
3. Timing path elements
4. Setup & Hold Checks
5. Slack Calculation
6. SDC Overview
7. Clocks
8. Generated Clocks
9. Boundary Constraints
|
Day1 Labs
· OpenTimer Introduction
· Understanding basics of OpenTimer
· Inputs to OpenTimer
· Constraints creation
· OpenTimer Run script
|
| Day2 Lectures
1. Other timing checks
2. Design Rule Checks
3. Latch Timing
4. STA Text Report
|
Day2 Labs
· Liberty Files and Understanding Lib Parsing
· Understanding SPEF file and SPEF parsing
· Understanding OpenTimer tool messages
· Understanding timing reports and timing graphs
|
| Day3 Lectures
1. Multiple Clocks
2. Timing arcs and Timing Sense
3. Cell Delays and Clock Network
4. Setup and Hold Detailed
5. STA Text Report
|
Day3 Labs
· Understanding full reg to reg STA analysis
· Understanding Slack computation
· Understanding and reviewing setup check report
|
| Day4 Lectures
1. Crosstalk and Noise
2. Operating modes and other variations
3. Clock Gating Checks
4. Checks on Async Pins
|
Day4 Labs
· Understanding clock gating check
· Understanding Async pin checks
|
| Day5 Lectures
1. Clock groups
2. Clock properties
3. Timing exceptions
4. Multiple modes
|
Day5 Labs
· Revisit slack computation
· Understand CRPR
· ECO insertion
|
