We should be able to dissect an ALU example and try to think how you would reuse that in a broader design flow, in a weeks’ time. This will be the beginning of a ramp-up “Learning by doing” session. This example covers Makefiles, Verilator, sandpiper and system verilog. So these things you should be able to bring together and comprehend the structure of a basic testbench. Then we need to take a step back and ask, if I do a processor design, how would you organize your processor? The typical process is you have super clusters, super clusters of clusters, and these clusters will have functional units which have very specific functionality.

Now what we are focusing on in this project is the arithmetic. The arithmetic is going to be a combinatorial transformation (not state machine) and this will be a very simple A to B flow where you can drive as many test vectors as you can. And there is no feedback loop or sequences which you need to worry about. So, let’s focus on that progression because you need to build the testbench environment in such a way that it can be quickly instantiated in a new functional unit.

What we are doing with tensorcore HDP project is we will have integer vector lane, it will have IEEE vector lane, it will have bfloat vector lane, it will have posit vector lane and this testbench structure should be productive such that if some new project comes in and says, we would like to do an FP9 design, then they should be able to quickly instantiate this testbench and start building their verilog

Here's the link to register (closes in 2 days)