FPGA and ASIC circuits are being worked on and the RTL development assumes ASIC design rules, with FPGA emulation as VnV. The Tensorcore is essentially a systolic array. In other projects, we indeed have a reconfigurable systolic array design, but for this project, the goal is to execute the tensor operators with fused-dot-product operators that are executed using a RISC-V V ISA. This provides more resource efficiency and
we can create TensorCores for training with the same design. Clocking depends on the number system and the implementation of the quire that is part of the FDP instruction.
We'll have designs that are single clock, to deeply pipelined multi-clock domains, and even self-timed pipelines. For this project, we have a shallow pipeline for the ALUs, and a multi-cycle quire. We are more interested in working with RNN and LSTM models as we are interested in abnormality detection algorithms with this project. Models will come from ONNX repositories. For this project, it is RISC-V V ISA v1.0 + FDP
instruction.
Interested participants can ask for project details by replying to this email
Program start/end date - 2nd January to 13th March, 2022