EDA

Visualization of the TLV Flow Library

{Project Code - VTFL}

This project adds visualization to components in the TL-Verilog FLow Library. It explores encapsulation of visualization and aspect-oriented visualization that decouples transaction visualization from component visualization.

Visualization for BaseJump STL

{Project Code - VBJS}

BaseJump STL is a library of SystemVerilog components used in the design of Black Parrot. This might be a good candidate for use of VIZ, both for Black Parrot and to augment BaseJump STL with generic visualization. This would explore the use of generic visualization of SystemVerilog components.

Visualization for basic digital logic instruction

{Project Code - VBDLI}

VIZ can be used to illustrate basic logic functions and concepts like logic gates, K-maps, pipelines, etc. This project would develop these visualizations. Bala Dhinesh implemented [basic logic gates]

TL-Verilog Editor Modes

{Project code - TVEM}

This general category of smaller projects improves the ecosystem for TL-Veriog development by creating editor support for various text editors and IDEs. Many editor modes already exist. A few possibilities include:
- Adding JavaScript editing support within the TL-Verilog mode for Code Mirror (used by Makerchip) for `viz` blocks
- Improved support for M4 editing in TL-Verilog mode for Code Mirror.
- GitHub support for TL-Verilog

EDA Microservices

{Project code - EDAM}

Makerchip currently supports simulation of Verilog and TL-Verilog code. It is expanding to support logic synthesis and other physical flows as well as support for other HDLs. This project will provide various microservices that run open-source eda tools that can be incorporated into Makerchip.

TL-Verilog Timing Reports

{Project code - TVTR}

This project will help designers to relate timing information from synthesis tools back to TL-Verilog's higher-level context (hierarchy, pipelines, and transactions). Scripts are needed to map RTL signal names to their original TL-Verilog names. This will be applied to timing reports from open source synthesis tools so timing information can be reported with respect to TL-Verilog source code.

DRC Test Generator 

{Project Code:DRCTG}

The goal is to develop a tool that takes DRC rules as an input in the MAGIC tech file format, and to generate for each of the rules at least 2 (or more if that makes sense for the specific rule) test-structure test-cases, a good test case (where the test-structure fulfills all DRC rules), and a bad test case (where the test-structure fulfills all other DRC rules but it breaks the given rule). Where it is useful, please add edge cases that could be discussed, or add rotated cases to check horizontal/vertical.

Reproducible Builds for OpenLane/TheOpenRoad 

{Project Code:RBFO}

Test for reproducibility, file any reproducibility issues with the respective project/subproject and Philipp Gühring, work on solutions

DRC Correction Engine: Analyze common DRC issues, automatically detect and solve them, integrate the DRC fixing functionality into Magic.     

{Project Code:DRCE}

Expand magic so that “drc why” can explain all potential layers for a given DRC failure without the annotated design rules

Liberty File HTML Report generation with tables and diagrams (Input: .LIB Output: HTML Report), compare 2 different liberty files, report similarities and differences.  

{Project Code:LFHR}

Develop a tool which takes a liberty file and generates a report about all the contents found in the file, it should display the tables and provide visualization (diagrams/graphs/3D) the values where possible. Display meaningful aggregation data like Minimum/Maximum values for tables. The second part is to enhance the tool to be able to compare 2 different liberty files. This should help the user to answer the following questions: Which parts of the files are equal? Which parts of the file are different? (e.g. are the power models missing in one of the files?) Are the same basic units used? (e.g. Micrometers vs. Nanometers)? Are the same Timing models used? (NLDM/CCS/ELDM/none)? Are the two liberty files possibly covering the same cell? (Do they have the same number of inputs and outputs?) How far off are the timing numbers? (E.g. Identical, within 1%, within 5%, within 10%) It would be great if this check would even be done in case of different timing models (e.g. NLDM/CCS/..) or when the whole file is using different basic units, or even when the timing models are covering slightly different data points.