VSD has done close to 20 chip tapeouts with 130nm from Skywater technology, but being a core STA engineer, there is one major thing that's missing in our tape-outs - Multi Corner timing analysis. Look at this image and you can imagine what all checks are done, before taping out an SoC. Now adding multiple PVT corners to every check increases the complexity, and that's why STA engineers are in great demand in the VLSI industry.
Participants completing this project with all necessary specs and checks in place - I don't see any reason for him/her not getting a job or profile change in the VLSI industry.
For freshers - this project will start from basics of STA, in a way it's needed in industry projects
For professionals - this project will start from an overview about STA, and you straight away enter into full-chip analysis
For both categories - you have an option to pause and let us know if you need help in any topic
Important Note - Interested participants can reply back to this email asking for a detailed description and we will send it across
Program start/end date - 2nd January to 13th March, 2022
Back-end
Performance characterization for VSDBabySoC comprising of RISC-V core, PLL and DAC
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Analyze and characterize RISC-V based VSDBabySoC for all timing corners, fix timing violations, ECO, implement and tapeout
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Thanks & Regards
Kunal P Ghosh
"A pessimist always sees difficulty in every opportunity, An optimist always sees opportunity in every difficulty"
