FPGA

1st CLaaS for Local FPGAs

{Project code - 1CLF}

1st Class supports web application communication with FPGA logic in the cloud. Support local FPGA use cases as well. This is useful for local applications as well as to support development that will ultimately be deployed to the cloud.

World CLaaS: Open FPGA Cloud

{Project code - WCOFC}

The vision is to enable individuals with FPGAs (World CLaaS Citizens) to share their hardware with the world

WARP-V Many-core Accelerator Microservice

{Project Code - WMAM}

It will provide a configurable, easily-modifiable many-core-on-FPGA hardware accelerator deployed as a microservice to accelerate web and cloud applications.

Front-end

TL-VHDL/TL-C/TL-Clash

{Project code - TVTCTC}

TL-Verilog is a Verilog implementation of TL-X, and currently Verilog is the only target language for TL-X. This project would see through the vision of layering transaction-level support on other languages. TL-VHDL would help to broaden the reach of the technology. TL-C would connect transaction-level design with System-C and therefore high-level synthesis. And, TL-Clash would explore the integration of transaction-level modeling with a stronger type system among other language benefits.

Fractal Valley

{Project code - FV}

This project turns the demo into a robust site showcasing the value of hardware-acceleration in the cloud and the fun world of fractals.

Verification

TL-UVM

{Project code - TLUVM }

In theory, TL-X should be applicable to UVM as well. Since UVM does not have open-source support, no one has yet tried. But it would be great to uncover issues and put together examples. It looks like Modelsim supports UVM and is freely available for Intel FPGAs. There might be other options.

RISC-V

Visualization of SweRV

{Project code - VOS}

The SweRV core is an open-source SystemVerilog RISC-V CPU core developed by Western Digital. It is an interesting core for college course and is being highlighted in the RVfpga course for one. Visualizing the operation of the core can greatly enhance the learning experience. This project aims to do so. SweRV is be built and simulated within Makerchip

Implementing other ISAs in WARP-V

{Project Code - IIW}

WARP-V currently has support for RISC-V, (incomplete) MIPS, and a toy educational ISA. PowerPC is also open now and could be implemented, in addition to any other open ISAs.

Neural Net

{Project code - NN}

We have created a simple configurable neural network model in TL-Verilog. This could follow a similar path to WARP-V w/ a configurator and cloud FPGA implementation. The WARP-V configurator is build in a modular fashion to support this easily.

EDA

Visualization of the TLV Flow Library

{Project Code - VTFL}

This project adds visualization to components in the TL-Verilog FLow Library. It explores encapsulation of visualization and aspect-oriented visualization that decouples transaction visualization from component visualization.

Visualization for BaseJump STL

{Project Code - VBJS}

BaseJump STL is a library of SystemVerilog components used in the design of Black Parrot. This might be a good candidate for use of VIZ, both for Black Parrot and to augment BaseJump STL with generic visualization. This would explore the use of generic visualization of SystemVerilog components.

Visualization for basic digital logic instruction

{Project Code - VBDLI}

VIZ can be used to illustrate basic logic functions and concepts like logic gates, K-maps, pipelines, etc. This project would develop these visualizations. Bala Dhinesh implemented [basic logic gates]

TL-Verilog Editor Modes

{Project code - TVEM}

This general category of smaller projects improves the ecosystem for TL-Veriog development by creating editor support for various text editors and IDEs. Many editor modes already exist. A few possibilities include:
- Adding JavaScript editing support within the TL-Verilog mode for Code Mirror (used by Makerchip) for `viz` blocks
- Improved support for M4 editing in TL-Verilog mode for Code Mirror.
- GitHub support for TL-Verilog

EDA Microservices

{Project code - EDAM}

Makerchip currently supports simulation of Verilog and TL-Verilog code. It is expanding to support logic synthesis and other physical flows as well as support for other HDLs. This project will provide various microservices that run open-source eda tools that can be incorporated into Makerchip.

TL-Verilog Timing Reports

{Project code - TVTR}

This project will help designers to relate timing information from synthesis tools back to TL-Verilog's higher-level context (hierarchy, pipelines, and transactions). Scripts are needed to map RTL signal names to their original TL-Verilog names. This will be applied to timing reports from open source synthesis tools so timing information can be reported with respect to TL-Verilog source code.