Look at this image and what if, I say, there are not one, but 2 bugs in the way the above report has been generated for post-layout? STA is very vast and beyond setup/hold timing. Working for so many years in STA, I still feel there is a lot to learn when technology shrinks. Do you want to work on a STA project for a real chip? This experience would be as good as industry work experience as
you will be involved in characterizing performance using full chip STA for real foundry.
VSD-HDP has 2 interesting projects in core STA and core Physical Design. When we use the word "core", that's industry grade projects. Check out "Projects List" tab in below link on steps to register for core projects
Category - Core STA project
Project name - Performance characterization for VSDBabySoC comprising of RISC-V core, PLL and DAC
Project code - PCVRPD
Project description - Analyze and characterize RISC-V based VSDBabySoC for all timing corners (tt, ss, ff), fix timing violations, ECO, implement and tapeout
Category - Core Physical design
Project name - rvmyth integration with PLL, DAC and SRAM using Sky13
Project code - RPDS
Project description - RISC-V based SoC design, physical design and tapeout using VSD Sky130 IPs
All the best and happy learning
