Published: Sun, 10/31/21
Hi There
Gentle reminder - 9hrs left to receive all VSD online VLSI courses at 90% to 95% discounted price
Here are the coupons-
All VLSI courses using FPGAs and Skywater 130nm PDKs
VSD – Mixed signal RISC-V based SoC on FPGA
https://www.udemy.com/course/vsd-mixed-signal-risc-v-based-soc-on-fpga/?couponCode=FD9E4A751C0E549F8346
VSD Intern – Mixed Signal Physical Design flow with OpenLANE/Sky130
https://www.udemy.com/course/vsd-intern-mixed-signal-physical-design-flow/?couponCode=B27B19142D650BF5E21D
VSD Intern – OpenRAM configuration for 4kB SRAM using Sky130
https://www.udemy.com/course/vsd-intern-openram-configuration-for-4kb-sram-using-sky130/?couponCode=3CC651CDF83AF5D16336
VSD Intern – Analog Bandgap Reference design usingSky130
https://www.udemy.com/course/vsd-intern-analog-bandgap-reference-design-using-sky130/?couponCode=5BF2C7433D1193D4D07B
VSD Intern – Analog comparator design usingSky130
https://www.udemy.com/course/vsd-intern-analog-comparator-design-using-sky130/?couponCode=A377255685A5308D1B1F
VSD Intern - DAC IP design using Sky130 PDKs - Part 1 (specifications)
https://www.udemy.com/course/vsd-intern-dac-ip-design-using-sky130-pdks-part-1/?couponCode=D6C1672ED95B3B2E1D3A
VSD Intern - DAC IP design using Sky130 PDKs - Part 2 (circuit design)
https://www.udemy.com/course/vsd-intern-dac-ip-design-using-sky130-pdks-part-2/?couponCode=162D322082BC8B0DA19A
VSD Intern - DAC IP design using Sky130 PDKs - Part 3 (layout)
https://www.udemy.com/course/vsd-intern-dac-ip-design-using-sky130-pdks-part-3/?couponCode=6BD889DA6F2A2C359F1C
VSD Intern – 10-bit DAC design using eSim and Sky130
https://www.udemy.com/course/vsd-intern-10-bit-dac-design-using-esim-and-sky130/?couponCode=D88B48C271779408A79E
VLSI Backend fundamental courses
Physical design
https://www.udemy.com/course/vlsi-academy-physical-design-flow/?couponCode=DD372FC4BA0754E3067B
Physical design webinar:
https://www.udemy.com/course/vsd-physical-design-webinar-using-eda-tool-proton/?couponCode=A2947FF79BDF048AD5B3
Clock tree synthesis – Part 1:
https://www.udemy.com/course/vlsi-academy-clock-tree-synthesis/?couponCode=2D8BA1D3831BD3729810
Clock tree synthesis – Part 2:
https://www.udemy.com/course/vlsi-academy-clock-tree-synthesis-part2/?couponCode=675AC05FB182A30D41A6
Signal Integrity:
https://www.udemy.com/course/vlsi-academy-crosstalk/?couponCode=4BAA94FD8805DF0A8CA0
Static timing analysis – Part 1:
https://www.udemy.com/course/vlsi-academy-sta-checks/?couponCode=DC606C7BCFC7170A0DC7
Static timing analysis – Part 2:
https://www.udemy.com/course/vlsi-academy-sta-checks-2/?couponCode=5F690FA83A9555022CCB
Timing ECO webinar:
https://www.udemy.com/course/vsd-timing-eco-engineering-change-order-webinar/?couponCode=2BD38888C9470B24EC4A
Circuit design and SPICE simulations – Part 1:
https://www.udemy.com/course/vlsi-academy-circuit-design/?couponCode=C8874B2109A5BF2B6DF8
Circuit design and SPICE simulations – Part 2:
https://www.udemy.com/course/vlsi-academy-circuit-design-part2/?couponCode=C9B60AFE22426E1FEAAD
Custom Layout:
https://www.udemy.com/course/vlsi-academy-custom-layout/?couponCode=CCCB28D61DAD60CF12DE
Library characterization – Part 1:
https://www.udemy.com/course/vlsi-academy-library-characterization-part-1/?couponCode=C3B76923F2F4EB0C0F57
Library characterization – Part 2:
https://www.udemy.com/course/vsd-library-characterization-and-modelling-part-2/?couponCode=90D67768F2959615BE33
TCL Scripting – Part 1:
https://www.udemy.com/course/vsd-tcl-programming-from-novice-to-expert/?couponCode=1D7778C52214C901F14E
TCL Scripting – Part 2:
https://www.udemy.com/course/vsd-tcl-programming-from-novice-to-expert-part-2/?couponCode=6203430F0FAE5FF10B73
RISC-V based theory and lab based online courses
RISC-V ISA:
https://www.udemy.com/course/vsd-riscv-instruction-set-architecture-isa-part-1a/?couponCode=760911044C79FAF186E3
https://www.udemy.com/course/vsd-riscv-instruction-set-architecture-isa-part-1b/?couponCode=31676CD127B9C161CC07
RISC-V based SoC Design:
https://www.udemy.com/course/vsd-making-the-raven-chip-how-to-design-a-risc-v-soc/?couponCode=77C73C51E1124D8473B5
RISC-V based Chip Physical Design:
https://www.udemy.com/course/vsd-soc-design-of-the-picorv32-riscv-micro-processor/?couponCode=1332B30F44E7DA7A8348
RISC-V based core Pipeline design:
https://www.udemy.com/course/vsd-pipelining-risc-v-with-transaction-level-verilog/?couponCode=34D00DF476C25D7D650B
All the best. Do well and keep me posted on progress.
Will be happy to help
Thanks